H - Electricity
01
L
356/23
H01L 29/76 (2006.01) H01L 29/423 (2006.01) H01L 29/812 (2006.01) H03D 7/12 (2006.01)
Patent
CA 2033380
ABSTRACT OF THE DISCLOSURE: In a dual gate FET of this invention, the number of points for supplying signal to a first gate electrode and the number of points for supplying signal to a second gate electrode are set to be optimal values so that a noise index is minimized. A difference in electrical length between each signal supply point of each of the first and second gate electrodes and the corresponding gate input terminal has a negligible magnitude with respect to a quarter wavelength of an input signal applied to the corresponding gate input terminal. The dual gate FET has a low-noise arrangement, and a microwave can be applied to either one of of the first and second gate electrodes, thereby obtaining, e.g., a low-noise mixer. In this case, a separator required upon use of a single gate FET can be omitted, thereby easily arranging a monolithic IC.
Marks & Clerk
Sumitomo Electric Industries Ltd.
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