Cache support architecture

G - Physics – 06 – F

Patent

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Details

354/223.1

G06F 12/02 (2006.01) G06F 12/08 (2006.01)

Patent

CA 2019727

Abstract of the Invention A method for identifying data stored in a shared memory resource of a data processing system to support compatibility of the processing system with CPU's with write-through caches, and CPU's with write-back caches, and CPU's without caches over a common data bus.

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