H - Electricity – 01 – L
Patent
H - Electricity
01
L
H01L 21/56 (2006.01) H01L 21/68 (2006.01) H01L 23/31 (2006.01)
Patent
CA 2356938
A dicing tape (11) is adhered to the lower surface of a silicon wafer (1) that has pillar-shaped electrodes (6). The silicon wafer (1) is cut along dicing streets, thereby making trenches (12) among the chip-forming regions of the wafer (1). Next, a seal film (13) is formed. The seal film (13) is cut, substantially along the centerlines of the trenches (12). A support tape (14) is adhered to the upper surface of the seal film (13). The dicing tape (11) is peeled off. Then, those parts of the seal film (13) that project from the lower surface of the silicon wafer (1) are polished and removed. The support tape (14) is peeled off. IC chips are thereby obtained. In each IC chip, the seal film covers and protects the upper surface and sides of the semiconductor substrate.
Le procédé de l'invention consiste à coller un ruban de découpage en dés (11), sur la surface inférieure d'une plaquette de silicium (1) dotée d'électrodes du type colonne (6), à découper la plaquette de silicium (1) le long de trajets de découpage en dés, de manière à former ainsi des tranchées (12) dans les régions -de la plaquette (1)- formant une puce, puis à former un film de scellement (13), à couper ce film (13), sensiblement le long des axes médians des tranchées (12), à coller un ruban support (14) sur la surface supérieure du film de scellement (13), à décoller le ruban de découpage en dés (13) puis à polir et éliminer les parties du film de scellement (13) qui saillent de la surface inférieure de la plaquette, (1), et à décoller enfin le ruban support (14), de manière à produire ainsi des puces à circuit intégré. Dans chacune de ces puces, le film de scellement recouvre et protège la surface supérieure et les côtés du substrat à semi-conducteur.
Casio Computer Co. Ltd.
Ridout & Maybee Llp
LandOfFree
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