Vector processing unit with reconfigurable data buffer

Details Vector processing unit with reconfigurable data buffer Vector processing unit with reconfigurable data buffer

G - Physics

06

F

G06F 13/20 (2006.01) G06F 9/38 (2006.01) G06F 15/78 (2006.01)

Patent

CA 2150518

Disclosed is an invention relating to a vector processing unit having a data buffer between a storage and a vector processor. Each of load data buffers is divided into four virtual buffers. Each virtual buffer can store 16 words of data which is 8 bytes per word. Accordingly, one load data buffer can use four 8 byte vector data when the vector length is 16, and 8 byte vector data as a unit when the vector length is 64. In addition, it is possible to use four 4 byte vector data when the vector length is 32, and 4 byte vector data as a unit when the vector length is 128 by compressing two 4 byte data into one 8 byte data and storing it in the load data buffer.

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