G - Physics – 06 – F
Patent
G - Physics
06
F
G06F 12/02 (2006.01) G06F 12/08 (2006.01)
Patent
CA 2052766
Methods and Apparatus for maintaining cache integrity in a computing system that includes a central processing unit (CPU), Random Access Memory (RAM), Read Only Memory (ROM), and a local memory controller for controlling cooperation between said CPU, RAM and ROM, wherein said computing system is capable of supporting a ROM mapped to RAM mode of operation, and further wherein said local memory controller, whenever said ROM mapped to RAM mode is enabled, (1) implements a snoop cycle to detect CPU write ROM operations and, upon detecting such an operation, (2) provides a cache invalidation signal to the CPU. The CPU utilizes the invalidation signal, along with the invalidation address on the local bus coupling the CPU and memory controller, to invalidate any cache data entry corresponding to the main memory address targeted by the CPU write ROM operation. The invalidation takes place while the write operation is in progress.
International Business Machines Corporation
Saunders Raymond H.
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