Clock signal regeneration method and apparatus

Details Clock signal regeneration method and apparatus Clock signal regeneration method and apparatus

H - Electricity

04

L

H04L 7/027 (2006.01) H03L 7/099 (2006.01) H04L 7/033 (2006.01)

Patent

CA 2138730

A clock signal regeneration method and apparatus by which the phase of a regenerated clock signal can be controlled with a step smaller than the width of one clock of a controlling clock signal to improve the accuracy in rate of the regenerated clock signal is disclosed. The apparatus comprises a timing extraction circuit for extracting, from the received data, a timing signal corresponding to a rate of the received data, a phase comparator for comparing the phases of the timing signal and a regenerated clock signal to produce a phase difference signal, an integrator for repetitively adding the phase difference signal at each clock of the regenerated clock signal in a cycle of a controlling clock signal whose frequency is higher than that of the timing signal to produce a phase difference integrated value for each of such adding operation, a sine wave regenerating ROM for converting the phase difference integrated value into amplitude information by which an amplitude of a sine waveform is represented in a digital value, a D/A converter for converting the amplitude information into an analog signal, and a comparator for comparing the analog signal with a reference voltage to produce a new regenerated clock signal.

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