Board errors correction apparatus

G - Physics – 06 – F

Patent

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Details

G06F 11/08 (2006.01) G06F 11/10 (2006.01) G11C 29/00 (2006.01)

Patent

CA 2131735

This invention includes an algorithm, which detects and identifies the error in each memory address of the Reduced Specification Integrated Memory chips (RSIMC). RSIMC with the same error pattern will then be grouped together along with the Error Correction Apparatus (ECA) for assembly into memory modules. ECA employs the redundant Error Correcting Algorithm which enables the rejected, fallout, audio grade, toy grade and other reduced specification memory chips to become computer grade compatible, such that the corrected RSIMC memory modules would function as normal memory modules for computer (or computer sub-systems) usages and applications.

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