Method of checking test program in duplex processing apparatus

Details Method of checking test program in duplex processing apparatus Method of checking test program in duplex processing apparatus

G - Physics

06

F

354/225

G06F 11/28 (2006.01) G06F 11/00 (2006.01) G06F 11/20 (2006.01) G06F 11/22 (2006.01) G06F 11/267 (2006.01)

Patent

CA 2002966

Abstract of the Disclosure Disclosed is a method of checking a test program in a duplex processing apparatus including two processors connected to each other through a failure acknowledge line and an interprocessor communication line and constituting an active system and a standby system, main memories connected to the two processors through buses, respectively, a queue connected to the buses which connect the processors to the main memories, and bus arbitors for controlling contention of a bus occupy right on the buses. In this method, normality of the test program is checked from an execution address of the test program executed by the standby processor under the control of the active processor. - 13 -

Affiliated with

Also associated with

Rating

Method of checking test program in duplex processing apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of checking test program in duplex processing apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of checking test program in duplex processing apparatus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1514906