Desynchronizer for a synchronous digital communications system

Details Desynchronizer for a synchronous digital communications system Desynchronizer for a synchronous digital communications system

H - Electricity

04

L

H04L 7/00 (2006.01) H04J 3/07 (2006.01) H04L 12/20 (2006.01)

Patent

CA 2271277

A desynchonizer for a synchronous digital communications system serves to recover a useful signal from a synchronous digital input signal. It comprises a buffer for temporarily storing the input signal, a write means for writing the input signal into the buffer, a clock-generating means for generating a clock signal, and a read means for reading the contents of the buffer at the recovered clock rate. According to the invention, the clock-generating means includes a calculating means for determining an average over the interval between two pointer actions of the input signal, and derives from the average a tuning signal which serves to adjust the recovered clock signal. In this manner, fitter caused by pointer actions which result from a constant offset of the effective bit rate of the received virtual containers is eliminated.

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