Cache unit capable of efficiently insuring cache coherence

Details Cache unit capable of efficiently insuring cache coherence Cache unit capable of efficiently insuring cache coherence

G - Physics

06

F

354/241

G06F 12/08 (2006.01) G06F 12/00 (2006.01)

Patent

CA 2000180

In a multiprocessor system including a plurality of cache units which are connected in common to a main storage (20) and to instruction processing units, respectively, each cache unit (3n) comprises a flag circuit (5n) divided into a plurality of flag bit areas (FA-1 to FA-M) which correspond to block areas (BA-1 to BA-M) of a cache memory (4n). Each flag bit area memorizes a flag bit corresponding to a block memorized in the corresponding block area to indicate presence or absence of one of memory blocks in a common memory area of the main storage in correspondence to the memorized block. Supplied with a cache clear request (CRn) from an n-th one (1n) of the instruction processing units, a cache clear circuit (6n) clears the cache memory so as to erase the memorized block when the flag bit indicates presence of the above-mentioned one of the memory blocks in the common memory area. When a block fetching circuit (7n) stores a memory block fetched from the main storage in the cache memory, a fetch detecting circuit (8n) detects whether the fetched memory block is present or absent in the common memory area. When the fetched memory block is present in the common memory area, a flag setting circuit (9n) sets the flag bit indicative of presence in the corresponding flag bit area.

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