Hit-less switching pointer aligner apparatus and method

H - Electricity – 04 – L

Patent

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Details

H04L 1/22 (2006.01) H04B 1/74 (2006.01) H04B 10/00 (2006.01) H04J 3/06 (2006.01) H04L 1/06 (2006.01) H04L 12/24 (2006.01) H04Q 11/04 (2006.01)

Patent

CA 2288578

A system and method are disclosed for processing digital signals in a telecommunications system that allow for hit-less switching between a first digital signal in which a first payload, a first pointer value, and a first frame are transported on a first channel, and a second digital signal in which a second payload identical to the first payload, a second pointer value, and a second frame are transported on a second channel. The present invention includes first and second pointer followers, first and second comparators, a delay buffer with control circuit, first, second, third and fourth multiplexers, and a pointer generator. The delay buffer control circuit further comprises a write counter, a read counter, a phase detector, and a leak-out mechanism for reinitializing the delay buffer. The present invention aligns the payloads of the first and second digital signals to allow for hit-less selection between them.

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