High speed asynchronous data interface

Details High speed asynchronous data interface High speed asynchronous data interface

H - Electricity

04

L

340/99

H04L 7/00 (2006.01) H04L 25/49 (2006.01) H04L 7/033 (2006.01) H04L 7/06 (2006.01)

Patent

CA 2012256

ABSTRACT:- A High Speed Asynchronous Data Interface A digital data interface for high speed asynchronous data transfer is described. The design is nominally intended for integration onto the component chips in communications systems. The system is described with respect to its realisation in CMOS IC technology. The techniques involved, however, may easily be applied to other technologies. The interface employs Manchester Bi- Phase Mark encoding of the clock and data to allow extraction of the clock and data signals at the receiver. Furthermore, use of this Manchester code allows code violations to be easily employed as frame markers for synchronisation means. The essence of the clock extraction and data detection circuit is the use of calibrated delay line elements to suppress data transitions within the coded input signal, thus allowing the clock transitions to be detected from which the clock is then generated.

Affiliated with

Also associated with

Rating

High speed asynchronous data interface does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High speed asynchronous data interface, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed asynchronous data interface will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1538617