Memory system comprising a plurality of memory controllers...

Details Memory system comprising a plurality of memory controllers... Memory system comprising a plurality of memory controllers...

G - Physics

06

F

G06F 13/18 (2006.01) G06F 12/00 (2006.01) G11C 7/00 (2006.01)

Patent

CA 2508655

The invention relates to a memory system which is configured with a plurality of memory controllers (SCx), disposed in parallel on a clocked bus (B), and memory chips (Fx) associated with the respective memory controllers (SCx). The system communicates via the bus (B) with a host system (HS) by means of operational memory commands using logical memory sector numbers. The inventive system is characterized in that for any memory operation requested by the host system (HS) the memory controller (SCx) affected with respect to a range of logical memory sector numbers (SCx) takes over the bus for communication with the host system (HS) by means of arbitration.

L'invention concerne un système de mémoire comportant plusieurs contrôleurs de mémoire (SCx) disposés en parallèle sur un bus cadencé (B), et les puces de mémoire (Fx) affectées auxdits contrôleurs de mémoire (SCx). Ledit système de mémoire communique par l'intermédiaire du bus (B) avec un système hôte (HS) contenant des instructions d'opérations de mémoire, à l'aide de numéros de secteurs de mémoire. Le système de mémoire selon l'invention est caractérisé en ce que le contrôleur de mémoire (SCx), concerné pour une zone de numéros de secteurs de mémoire logiques, relaye le bus pour la communication avec le système hôte (HS) par arbitrage, en cas de requête d'opération de mémoire par le système hôte (HS).

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