Test interface for a digital circuit

Details Test interface for a digital circuit Test interface for a digital circuit

G - Physics

01

R

G01R 31/28 (2006.01)

Patent

CA 2057339

An arrangement is disclosed that is added to digital circuit device for providing a way of easily verifying that the device's input and output circuits are operating and connected properly. The arrangement implements a test mode in which a simple exercising sequence is placed on any single input of a defined sequential group of device pins. A resultant output can be observed on the next occurring output and all subsequent outputs of the defined sequential group.

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