Multiple stage pipeline processor including reconfigurable...

Details Multiple stage pipeline processor including reconfigurable... Multiple stage pipeline processor including reconfigurable...

H - Electricity

04

N

H04N 7/50 (2006.01) G06F 9/06 (2006.01) G06F 12/02 (2006.01) G06F 12/04 (2006.01) G06F 12/06 (2006.01) G06F 13/16 (2006.01) G06F 13/28 (2006.01) G06T 9/00 (2006.01) H04N 7/26 (2006.01)

Patent

CA 2145158

A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

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