Error correction code with write error preservation for...

Details Error correction code with write error preservation for... Error correction code with write error preservation for...

G - Physics

06

F

G06F 11/20 (2006.01) G06F 11/10 (2006.01)

Patent

CA 2130408

ABSTRACT A computer system and method of using the same is provided which system has a CPU, a bus, and add-on memory. The CPU has parity generation and detection capabilities but does not necessarily have error correction capabilities. The present invention provides error correction capabilities in add-on memory or in association with the add-on memory which allows error correction of single bit read errors from the add-on memory and also allows for the detection of multiple bit read errors and the detection of write errors by byte location of the write errors.

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