Bus arbitration between an input/output device and a...

Details Bus arbitration between an input/output device and a... Bus arbitration between an input/output device and a...

G - Physics

06

F

G06F 13/42 (2006.01) G06F 13/16 (2006.01)

Patent

CA 2163850

In an information processing system comprising an input/output device, a main memory device, a processing device including a first-in first-out type write-in buffer, and a bus connecting thereamong, the first-in first-out type write-in buffer comprises a flag bit holding area for holding a bus release request signal from the input/output device as a flag bit to produce the flag bit as a flag signal. The bus arbitration circuit determines the bus available right so as to grant a priority right for data write-in processing by the input/output device rather than data write-in processing by the processing device when the bus arbitration circuit receives the flag signal. The bus arbitration circuit determines the bus available right on the basis of the bus release request and the flag signal.

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