System packet interface

Details System packet interface System packet interface

H - Electricity

04

Q

H04Q 11/00 (2006.01)

Patent

CA 2521659

An apparatus including a first integrated circuit (IC) (202), a second IC (204), and an interface coupling the first IC to the second IC (200). The interface transfers payload control information between the first IC and the second IC utilizing a number of data transmission lines. On the clock cycle transition following the transfer of payload control information, the interface transfers packetized data between the first IC and the second IC at a data rate of at least approximately 20Gbps utilizing the same transmission lines. A one-bit control signal is used by the interface to identify when payload control information is present on all of the data transmission lines.

L'invention concerne un dispositif comprenant un premier circuit intégré (IC) (202), un second IC (204), et une interface de couplage entre les deux IC (200). L'interface transfère l'information de contrôle de données utiles entre les premier et second IC, via un certain nombre de lignes de transmission de données. Sur la transition de cycle d'horloge qui suit le transfert de ladite information, l'interface transfère des données par paquets entre les premier et second IC à un débit d'au moins environ 20 Gbps via les lignes de transmission en question. Un signal de contrôle à un bit est utilisé par l'interface pour l'identification de la présence de l'information considérée sur l'ensemble des lignes de transmission.

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