Semiconductor device

Details Semiconductor device Semiconductor device

G - Physics

11

C

G11C 11/34 (2006.01) G11C 11/403 (2006.01) G11C 11/405 (2006.01) H01L 27/108 (2006.01)

Patent

CA 2315434

A semiconductor device capable of reducing a cell area without affecting the accuracy, capable of reducing the number of interconnection layers, and capable of realizing a hybrid circuit of a memory cell and peripheral circuit easily and at a low cost, including a bit line, a word line, control gate line, a capacitor with a first electrode connected to the word line, a read transistor comprising an NMOS connected between the bit line and a predetermined potential point and with a gate electrode connected to a second electrode of a capacitor, and a write transistor comprising an NMOS connected between the bit line and the second electrode of the capacitor and with a gate electrode connected to the control gate line.

Un dispositif semi-conducteur capable de réduire une zone cellulaire sans en affecter la précision, capable de réduire le nombre de couches d'interconnexion et capable de réaliser facilement et à moindre coût un circuit hybride d'une mémoire cellulaire et d'un circuit périphérique, comprenant un canal bit, un canal mot, un canal porte de contrôle, un condensateur muni d'une électrode reliée au canal mot, un transistor (lecture) comprenant un MOS à canal N connecté entre le canal bit et un point de puissance muni d'une électrode grille connectée à une seconde électrode d'un condensateur, et un transistor (écriture) comprenant un MOS à canal N connecté entre le canal bit et la deuxième électrode du condensateur et muni d'une électrode grille connectée au canal porte de contrôle.

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