Computationally efficient convolutional coding with...

Details Computationally efficient convolutional coding with... Computationally efficient convolutional coding with...

H - Electricity

04

L

H04L 1/00 (2006.01)

Patent

CA 2689292

An error coding circuit comprises a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits, an interleaver circuit for interleaving parity bits within each group of parity bits, and a rate-matching circuit for outputting a selected number of the interleaved parity bits ordered by group to obtain a desired code rate.

La présente invention concerne un circuit de codage d'erreurs comportant un codeur convolutionnel non systématique permettant de coder un flux binaire d'entrée pour produire au moins deux groupes de bits de parité, un circuit entrelaceur permettant l'entrelacement de bits de parité au sein de chaque groupe de bits de parité, et un circuit de fixation de paramètres d'adaptation de débit permettant d'émettre en sortie un nombre sélectionné de bits de parité ordonnés par groupe pour obtenir un débit de code souhaité.

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