Systems and methods for a disk controller memory architecture

G - Physics – 06 – F

Patent

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G06F 3/06 (2006.01)

Patent

CA 2370596

The present invention is related to systems and methods for a disk controller memory. In one embodiment, a mass storage device is interfaced to a computer via an I/O bus using a mass storage device controller. The mass storage device controller includes a processor and a buffer memory configured to receive data from the mass storage device and the I/O bus. In addition, the controller includes a memory circuit coupled to the buffer memory and the processor. The memory circuit is configured to operate as a first-in-first-out memory during at least a first transfer of data between the memory circuit and the buffer memory. For example, the memory may be configured to operate as either as a random access memory or a FIFO during at least a first transfer of data between the memory circuit and the processor.

L'invention concerne des systèmes et des procédés destinés à la mémoire d'un contrôleur de disque dur. Dans un mode de réalisation, une mémoire de grande capacité est reliée à un ordinateur par un bus d'entrée-sortie à l'aide d'un contrôleur de mémoire de grande capacité. Ledit contrôleur de mémoire de grande capacité comprend un processeur et une mémoire tampon conçus pour recevoir les données transmises par la mémoire de grande capacité et par le bus d'entrée-sortie. De plus, ledit contrôleur comprend un circuit de mémoire couplé à la mémoire tampon et au processeur. Ledit circuit de mémoire est configuré de manière à fonctionner comme une mémoire FIFO durant, au moins, le premier transfert de données entre le circuit de mémoire et la mémoire tampon. Par exemple, la mémoire peut être configurée de manière à fonctionner soit comme une mémoire vive soit comme une mémoire FIFO, durant, au moins, le premier transfert de données entre le circuit de mémoire et le processeur.

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