Clock recovery circuit employing delay-and-difference...

Details Clock recovery circuit employing delay-and-difference... Clock recovery circuit employing delay-and-difference...

H - Electricity

04

L

H04L 7/033 (2006.01) H04L 25/06 (2006.01) H04L 27/22 (2006.01) H04L 7/04 (2006.01)

Patent

CA 2154858

A clock recovery circuit receives an input signal having an eye pattern and takes differences at certain intervals to generate a differential signal. A set of comparators detect timings at which the differential signal matches different levels, and generate pulse signals at these timings. A classifying circuit classifies trajectories of the differential signal by detecting certain sequences of these pulse signals, and activates a gate signal when these sequences are detected. A delay circuit delays one of the pulse signals to create a delayed signal. A gate circuit outputs the delayed signal as a timing signal when the gate signal is active. A phase-locked loop generates a clock signal synchronized to the timing signal.

Affiliated with

Also associated with

Rating

Clock recovery circuit employing delay-and-difference... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock recovery circuit employing delay-and-difference..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock recovery circuit employing delay-and-difference... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1640320