System and method for providing an arbitrated memory bus in...

Details System and method for providing an arbitrated memory bus in... System and method for providing an arbitrated memory bus in...

G - Physics

06

F

G06F 13/36 (2006.01)

Patent

CA 2492970

A computing system having at least one microprocessor and a memory subsystem coupled to the at least one microprocessor. A memory controller is coupled to manage memory transactions between the memory subsystem and the at least one microprocessor. At least one arbitration port is coupled to the memory controller and configured to receive an external arbitration signal.

L'invention concerne un système informatique comprenant au moins un microprocesseur et un sous-système de mémoire couplé audit microprocesseur. Un contrôleur de mémoire est couplé afin de gérer des transactions de mémoire entre le sous-système de mémoire et le microprocesseur. Au moins un port d'arbitrage est couplé au contrôleur de mémoire et configuré afin de recevoir un signal d'arbitrage extérieur.

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