Method of functionally testing cache tag rams in...

Details Method of functionally testing cache tag rams in... Method of functionally testing cache tag rams in...

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G06F 11/30 (2006.01) G06F 12/08 (2006.01) G11C 29/00 (2006.01) G11C 29/10 (2006.01) G11C 29/44 (2006.01) G06F 12/00 (2006.01)

Patent

CA 2033449

METHOD OF FUNCTIONALLY TESTING CACHE TAG RAMS IN LIMITED-ACCESS PROCESSOR SYSTEMS Abstract of the Disclosure A method of functionally testing cache tag RAMs in processor systems where the kernel is typically inaccessible is disclosed. A test program first determines whether a fault exists at all within the cache tag RAM. If a fault is determined to exist, the faulty RAM location is exercised by sequentially applying patterns of ones and zeros until the pattern of bits actually present at the faulty tag RAM location is determined. A comparison of this pattern of bits with the expected bit pattern provides information as the precise location of the fault so as to permit replacement of defective chips.

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