H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/176, 356/192
H01L 21/42 (2006.01) H01L 21/3105 (2006.01)
Patent
CA 2032763
A method of fabricating multilevel semiconductor wafers including a spin-on glass planarization layer is described. Prior to sputtering of the interconnect layer and after application of the spin-on glass layers the wafer is exposed to an intense glow discharge in such a way that it is bombarded in at least a partial vacuum with ions and/or electrons and/or photons while at a temperature that is between 400°C and 550°C and that is at least 25°C higher than the temperature to which the wafer is to be subjected during the subsequent sputtering step. In this way undesirable molecules can be desorbed from the spin-on glass layer so that they do not interfere with the subsequent sputtering step.
Marks & Clerk
Zarlink Semiconductor Inc.
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