Low leakage and data retention circuitry

Details Low leakage and data retention circuitry Low leakage and data retention circuitry

H - Electricity

03

K

H03K 19/0175 (2006.01) H03K 17/687 (2006.01) H03K 19/20 (2006.01)

Patent

CA 2595375

An integrated circuit includes first circuitry (1010) and sleep transistor circuitry (SL3). The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

L'invention porte sur un circuit intégré comportant un premier circuit et des circuits de veille transistorisés. Le premier circuit reçoit des signaux d'entrée, les traite et les conserve dans un état de veille à faibles fuites. Les circuits de veille transistorisés, sont reliés au premier circuit et reçoivent un signal de veille de tension négative. Lesdits circuits réduisent la consommation du premier circuit à l'état de veille en raison des faibles fuites sur le signal de veille, tout en conservant les données dans le premier circuit.

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