Time division multiplexer/demultiplexer with deterministic...

Details Time division multiplexer/demultiplexer with deterministic... Time division multiplexer/demultiplexer with deterministic...

H - Electricity

04

J

363/19

H04J 3/02 (2006.01) H04J 3/16 (2006.01)

Patent

CA 2028142

A frame building procedure for use in time division multiplexer systems for building a frame with N slots numbered #1,#2, #3,...,#N in increasing time order. A slot assignment sequence is generated in successive iterations I by initially assigning slot #1 as the first assignment in the sequence (50). N/2I is added to the slot number of all previously assigned slots during each iteration (54). Additionally, during each iteration, I is incremented by unity (59). The iterations are performed until all N slots are assigned when N/2I = 1 (58).

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