Register and arithmetic logic unit

Details Register and arithmetic logic unit Register and arithmetic logic unit

G - Physics

06

F

354/166

G06F 7/38 (2006.01) G06F 7/50 (2006.01) G06F 7/57 (2006.01) G06F 9/30 (2006.01) G06F 9/302 (2006.01)

Patent

CA 2007059

REGISTER AND ARITHMETIC LOGIC UNIT ABSTRACT Register and arithmetic logic apparatus for use in processing digital data and which provides a split pipeline architecture that operates on multiple data formals. A register file (444) is employed to store data words. An arithmetic logic unit (450) processes the data words by means of two parallel arithmetic logic units (450a, 450b) that provide fixed point and floating point arithmetic processing operations, respec- tively. The two parallel arithmetic logic units (450a, 450b) permit processing of a plurality of predetermined data processing formats, including dual 16 bit fixed point, 32 bit fixed point, 32 bit floating point and logical data processing formats. Post-pro- cessing registers (454, 456) provide for a limiter/shifter register, a length selectable first in, first out buffer for controlling the length of the register pipeline, and logic which provides for queuing of the processed data words. The register file (444) and the fixed point arithmetic logic unit (450a) may be selectively coupled together to function as an accumulator. This function permits processing of the data words such that two 32 bit data words are accumulated into a 64 bit data word, or the dual 16 bit data words are accumulated into two 32 bit data words. Processing using the dual 16 bit format employs a potential overflow scheme that permits a variety of gignal pro- cessing algorithms to function with relatively compact code.

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