Bicmos process

Details Bicmos process Bicmos process

H - Electricity

01

L

356/149

H01L 21/331 (2006.01) H01L 21/336 (2006.01) H01L 21/8249 (2006.01)

Patent

CA 2024640

A BiCMOS PROCESS Abstract of the Invention A method for manufacturing a BiCMOS device includes providing a semiconductor substrate including first and second electrically isolated device regions. A layer of insulating material is formed over the first device region, and a layer of conductive material is formed conformally over the device. Portions of the conductive layer are removed to leave a base contact on the surface of the second device region and an insulated gate contact over the surface of the first device region. A FET is formed in the first device region having a channel under the insulated gate. A vertical bipolar transistor is formed in the second device region having a base region contacting the base contact.

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