Signal delay apparatus employing a phase locked loop

Details Signal delay apparatus employing a phase locked loop Signal delay apparatus employing a phase locked loop

H - Electricity

03

K

H03K 5/135 (2006.01) H03K 5/13 (2006.01) H03K 5/14 (2006.01) H03K 5/15 (2006.01) H03L 7/081 (2006.01) H03L 7/089 (2006.01) H03K 5/00 (2006.01)

Patent

CA 2073888

An apparatus is provided for delaying digital data signals by fixed amounts within an integrated circuit. A delay lock loop includes an adaptive delay line, a phase detector and an integrator. The integrator provides control signals cp, cn for controlling the delay line, in dependence upon the relative phase of a reference clock signal ?o and a delayed clock signal ?n. The delay line includes a plurality of delay cells. By maintaining a phase relationship ?n = ?o + 360° one clock cycle, Tc, delay through the delay line is provided. Thus each delay cell provides Tc/n delay. By placing identical cells in signal paths elsewhere on a chip, fixed delays can be introduced which are controlled by the delay lock loop. A harmonic lock detector connected to a plurality of clock phase taps from the delay line detects harmonic lock conditions for second through tenth harmonics, resetting the delay lock loop in the event of harmonic lock.

Affiliated with

Also associated with

Rating

Signal delay apparatus employing a phase locked loop does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Signal delay apparatus employing a phase locked loop, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Signal delay apparatus employing a phase locked loop will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1686668