Receiver having clock phase memory for receiving short...

Details Receiver having clock phase memory for receiving short... Receiver having clock phase memory for receiving short...

G - Physics

06

F

G06F 13/16 (2006.01) H04J 3/06 (2006.01) H04L 7/10 (2006.01) H04L 7/00 (2006.01) H04L 7/04 (2006.01)

Patent

CA 2108640

A clock phase signal of each time slot of a TDM signal is stored into a corresponding memory location and a clock phase signal of a subsequent time slot is read from a memory location corresponding to the subsequent time slot for recovering clock pulses. A decoder is synchronized with the clock pulses for decoding an encoded digital signal of each time slot to produce a decoded signal. The error rate of the decoded signal of each time slot is decoded and compared with a prescribed value. When the detected error rate is determined to be higher than the prescribed value, the write operation of the memory is disabled to prevent the clock phase signal stored in a memory location corresponding to the decoded signal from being overwritten with a subsequent clock phase signal.

Un signal de phase d'horloge associé à chaque intervalle de temps d'un signal MRT (multiplexage temporel) est stocké dans une position mémoire correspondante et un signal de phase d'horloge associé à un intervalle de temps suivant est lu dans une position mémoire correspondant à l'intervalle subséquent dans le but de récupérer des impulsions d'horloge. Un décodeur est synchronisé avec les impulsions d'horloge pour décoder un signal numérique codé de chaque intervalle de temps et produire ainsi un signal décodé. Le taux d'erreur du signal décodé de chaque intervalle de temps est décodé et comparé à une valeur prescrite. Lorsque ledit taux d'erreur s'avère supérieur à ladite valeur, l'enregistrement dans la mémoire est invalidé pour que le signal de phase d'horloge stocké dans une position mémoire correspondant au signal décodé ne soit pas remplacé par un signal de phase d'horloge subséquent.

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