H - Electricity – 01 – L
Patent
H - Electricity
01
L
H01L 27/02 (2006.01) G11C 11/40 (2006.01) H01L 21/28 (2006.01) H01L 21/70 (2006.01) H01L 29/423 (2006.01) H01L 29/78 (2006.01) H01L 29/788 (2006.01)
Patent
CA 2051686
A single transistor electrically programmable and erasable memory cell (10) has a substrate (12) of a semi- conductor material of a first-conductivi- ty type (18). Within the substrate are de- fined source (16), drain (14), regions with a channel region (18) therebe- tween. A first insulating layer (20) is disposed over the subtract (12) and over the source (16) channel (18) and drain (14) regions. An electrically conductive, re-crystallized floating gate (22) is dis- posed over the first-insulating layer (20) and extends over a portion of the chan- nel region (18) and over a portion of the drain region (14) to maximize capaci- tive coupling therewith. A second insu- lating layer (25) has a top wall portion (24) over the floating gate (22) and a side wall portion (26) immediately adja- cent to the floating gate (22) and has a thickness which permits the Flowler- Nordheim tunneling of charges therethrough. An electrically conductive control gate (29) has two electrically connected sections: a first section (30) is over the first insulating layer (20) and is immediately adjacent to the side-wall portion (26) of the second in- sulating layer (25). The first section (30) extends over a portion of the channel region (18) and over the source region (16). A sec- ond section (28) is disposed over the top wall portion (24) of the second insulating layer (25) to minimize capacitive coupling with the floating gate (22).
Jenq Ching-Shi
Yeh Bing
Silicon Storage Technology Inc.
Smart & Biggar
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