Timing arrangement for computers

Details Timing arrangement for computers Timing arrangement for computers

G - Physics

06

F

354/230.86

G06F 1/04 (2006.01) G06F 1/14 (2006.01) G06F 9/22 (2006.01)

Patent

CA 1075821

ABSTRACT OF THE DISCLOSURE The invention provides a timing arrangement for a computer for determining timing of a microprogram and for deter- mining starting times of operations performed in real time, for example clock interrupt in the program. The arrangement comprises a common clock oscillator which generates timing signals for a control unit of the computer and for real time measuring circuits. A frequency divider is arranged to divide the frequency of the clock oscillator in such a manner that the frequency is adapted to the period length between the operations performed in real time, the frequency of the clock oscillator being an integral multiple of the step pulse frequency intended for the time measur- ing circuits. The dividing ratio of said frequency divider is adjustable in such a way that it is possible, by carrying out division of the frequency of the clock oscillator by an integer, to maintain at a constant value the timing signals of the real time measuring circuits, upon a frequency change of the timing signals of the computer control unit depending on working conditions. Thus the number of working cycles per step pulse interval is always an integer.

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