Register set used in multithreaded parallel processor...

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G06F 9/00 (2006.01) G06F 9/30 (2006.01) G06F 9/312 (2006.01) G06F 9/315 (2006.01) G06F 9/32 (2006.01) G06F 9/38 (2006.01) G06F 12/00 (2006.01)

Patent

CA 2386558

A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts (THREAD_3 ... THREAD_0). The processor maintains execution threads (THREAD_3 ... THREAD_0). The execution threads (THREAD_3 ... THREAD_0) access a register set organized into a plurality of relatively addressable windows of registers that are relatively addressable per thread (THREAD_3 ... THREAD_0).

L'invention concerne un processeur multifilière à base matérielle en parallèle. Le processeur comprend notamment un processeur universel qui coordonne des fonctions système et une pluralité de micro-moteurs qui supportent de nombreuses unités d'exécution de matériel ou de contextes (unité d'exécution_3 unité d'exécution_0). Le processeur conserve les unités d'exécution (unité d'exécution_3 unité d'exécution_0). Ces unités accèdent à un ensemble de registres organisé en une pluralité de fenêtre de registres relativement adressables qui le sont par unité d'exécution (unité d'exécution_3 unité d'exécution_0).

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