Multi-channel encoder/decoder

Details Multi-channel encoder/decoder Multi-channel encoder/decoder

H - Electricity

04

L

H04L 29/10 (2006.01) H04L 12/56 (2006.01) H04L 29/06 (2006.01) H04L 29/08 (2006.01)

Patent

CA 2224392

A multi-channel network device, for interfacing between a plurality of physical data links and a control processor, with each physical data link characterized by a data stream of data packets communicated according to a data link control protocol. The device includes a receive section where incoming data packets are each received in at least one data segment on one of a plurality of receive-side line interfaces. A receive-side priority encoder circuit services incoming data segments arriving on the receive-side line interfaces and pipelines the incoming data segments to a receive-side channel assigner circuit for channel assignment. A receive-side data processor coupled to the receive-side channel assigner circuit decodes ones of the incoming data segments. A receive-side packet buffer processor coupled to the receive-side data processor stores incoming data segments in receive-side channel FIFO buffers. A receive-side packet management circuit coupled to the receive-side packet buffer processor transfers incoming data segments from the receive-side channel FIFO buffers to an external control processor via a control processor interface. In a transmit section of the device, a transmit-side packet management circuit sorts blocks of outgoing data, each having at least one outgoing data segment and awaiting transmission from the control processor to ones of the physical data links, into linked lists. Each linked list is associated with one of a plurality of outgoing data channels in the transmit section. The transmit-side packet management circuit is operative to communicate each block of outgoing data from the control processor to a transmit-side packet buffer processor based on requests for outgoing data transmitted by transmit-side line interfaces. The transmit-side packet buffer processor is operative to store outgoing data segments of each block of outgoing data received from the transmit-side packet management circuit in transmit-side channel FIFO buffers. The transmit-side line interfaces are operative to communicate with the physical data links and are monitored for requests for outgoing data by a transmit-side priority encoder circuit. The transmit-side packet buffer processor retrieves outgoing data segments stored in the transmit-side channel FIFO buffers according to the order of the requests for outgoing data, for subsequent transmission by the associated transmit-side line interfaces to ones of the physical data links. A transmit-side data processor encodes ones of the outgoing data segments retrieved from the transmit-side channel FIFO buffers. Retrieved outgoing data segments are pipelined to a transmit-side channel assigner for channel assignment prior to transmission on the appropriate transmit-side line interfaces.

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