Integrating metal with ultra low-k dielectrics

Details Integrating metal with ultra low-k dielectrics Integrating metal with ultra low-k dielectrics

H - Electricity

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H01L 21/44 (2006.01) H01L 21/288 (2006.01) H01L 21/31 (2006.01) H01L 21/321 (2006.01) H01L 21/469 (2006.01) H01L 21/768 (2006.01)

Patent

CA 2421799

In forming a layer of a semiconductor wafer (100), a dielectric layer is deposited on the semiconductor wafer. The dielectric layer (208) includes material having a low dielectric constant. Recessed (210) and non-recessed (211) areas are formed in the dielectric layer. A metal layer is deposited on the dielectric layer to fill the recessed areas and cover the non-recessed areas. The metal layer is then electropolished to remove the metal layer covering the non-recessed areas while maintaining the metal layer in the recessed areas.

Lors de la formation d'une couche d'une plaquette en semi-conducteur (1) une couche diélectrique est déposée sur la plaquette en semi-conducteur. La couche diélectrique (204) contient un matériau ayant une faible constante diélectrique. Des zones évidées (210) et non évidées (211) sont formées dans la couche diélectrique et une couche métallique recouvre les zones non évidées. La couche métallique est ensuite électropolie pour éliminer la couche de métal recouvrant les zones non évidées tout en gardant la couche de métal dans les zones évidées.

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