Method and apparatus for testing multi-port memory

Details Method and apparatus for testing multi-port memory Method and apparatus for testing multi-port memory

G - Physics

11

C

G11C 29/00 (2006.01) G11C 8/16 (2006.01) G11C 29/28 (2006.01)

Patent

CA 2219844

A method of and apparatus for testing multi-port memory performs a shadow read to an adjacent memory cell concurrent with a write operation associated with typical read-write testing. In the presence of a bit wire short or a word wire short, the concurrent read of an adjacent memory cell will cause the value of that cell to be corrupted. The corrupted value is then found by the read-write testing. Consequently, the testing takes no longer than read-write testing. In addition, the testing scheme can be modified for memory with read only ports. An embodiment of the apparatus employs an exclusive OR gate on the least significant bit of the test row address line to generate the shadow read address.

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