Method of and circuit for synchronizing data

Details Method of and circuit for synchronizing data Method of and circuit for synchronizing data

H - Electricity

04

L

H04L 7/00 (2006.01) H04J 3/07 (2006.01)

Patent

CA 2069092

Asynchronous DS-1 data is byte synchronized and converted to the SONET VT1.5 format by storing the DS-1 data in a store (20) from which it is read in dependence upon a gapped clock signal (40) which is produced by gapping a first gapped clock signal (48) with a ratio of 208/193, which is the ratio of VT SPE bits per frame to DS-1 bits per frame. The first gapped clock sig- nal is produced by gapping a VT1.5 synchronous clock signal (46). A frequency difference between the first gapped clock signal and the asynchronous data rate, multiplied in a frequency multiplier (26) by the ratio of 208/193, is monitored by comparing the counts of modulo-208 counters (84, 86), and, independence upon the monitored frequency difference, the gapping of the syn- chronous clock signal is controlled to achieve positive or negative stuffing and hence to compensate for the frequency difference.

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