Clock generator and synchronizing method

Details Clock generator and synchronizing method Clock generator and synchronizing method

H - Electricity

03

K

H03K 5/13 (2006.01) G06F 1/10 (2006.01) H03L 7/085 (2006.01) H03L 7/14 (2006.01) H04J 3/06 (2006.01) H04L 7/033 (2006.01) H03L 7/093 (2006.01) H04L 7/00 (2006.01) H04Q 11/04 (2006.01)

Patent

CA 2276815

Network elements of a synchronous digital communications system have a clock generator for generating a clock signal locked to an input signal. Such a clock generator comprises a tunable oscillator (OSC) and a phase comparator (PK) for comparing the phase of the input signal (IN) with the phase of the clock signal (CLK) and for generating a correction signal which serves to tune the oscillator (OSC). To avoid phase transients due to interruptions and disturbances in the input signal (IN), means (WD) are provided for determining an expectancy window, for deciding whether the correction signal lies within the expectancy window, and for tuning the oscillator with the correction signal if the correction signal lies within the expectancy window.

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