Low inductance conductor topography for mosfet circuit

H - Electricity – 01 – L

Patent

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Details

H01L 23/52 (2006.01) H01L 23/495 (2006.01) H01L 23/522 (2006.01) H01L 23/64 (2006.01) H01L 29/41 (2006.01) H01L 29/417 (2006.01) H01L 29/45 (2006.01) H01L 29/78 (2006.01)

Patent

CA 2161153

Lead inductance of a power MOSFET circuit layouts is effectively reduced a 'vertically' parallel terminal lead configuration that serves to cancel magnetic flux linkage between adjacent leads, thereby reducing the effective inductance in terminal leads to the gate, source and drain regions of the circuit. Drain leads are arranged as vertically parallel pair of flat conductors, that overlie one another on opposite sides of a thin strip of insulating material. The substantially identical vertical geometry projection of these flat conductors upon one another on opposite sides of a thin strip of insulating material, forward and return current through the flat conductors are caused to be in close proximity with each other, so as to thereby effect magnetic flux linkage cancellation and significantly reducing the effective inductance of the source and drain conductors.

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