Method for planarization of submicron vias and the...

H - Electricity – 01 – L

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

H01L 21/70 (2006.01) C23C 14/04 (2006.01) H01L 21/283 (2006.01) H01L 21/285 (2006.01) H01L 21/321 (2006.01) H01L 21/768 (2006.01) H01L 23/535 (2006.01)

Patent

CA 2159648

Submicron vias (12-14) are filled by sputter deposition of a conductor such as aluminum (15) onto a substrate (11) such as silicon or silicon oxides. The aluminum film (15) is deposited at a first lower temperature and then the temperature is increased. The differential coefficient of thermal expansion of the substrate (11) relative to the metal (15) conductor forces the conductor to expand into the via (12- 14). Maintaining an effective thickness (1+) and controlling the temperature increase from the first temperature to the second temperature, effectively and reliably fills submicron vias having aspect ratios up to 4. The present invention is particularly useful with filling vias having re-entrant angles up to 20°.

LandOfFree

Say what you really think

Search LandOfFree.com for Canadian inventors and patents. Rate them and share your experience with other people.

Rating

Method for planarization of submicron vias and the... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for planarization of submicron vias and the..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for planarization of submicron vias and the... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFCA-PAI-O-1772124

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.