Communication circuit fault detector

H - Electricity – 04 – L

Patent

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340/76

H04L 1/00 (2006.01) H04L 1/24 (2006.01)

Patent

CA 2017579

A communication circuit fault detector tests a communication circuit by using a sequence generator to generate a test signal, a memory circuit to temporarily store the test signal, and a multiplexer to multiplex the test signal and an input data signal into the communication circuit. A timing generator drives the communication circuit at a rate higher than the normal communication rate, enabling the data signal and test signal to be sent through the communication circuit simultaneously. A demultiplexer demultiplexes the output signal from the communication circuit into an output data signal and a returned test signal. A comparator compares the returned test signal with the test signal stored in the memory circuit and generates a result signal indicating whether they match.

L'invention est un détecteur de défaillances dans les circuits de communication qui utilise un générateur de signaux de vérification, un circuit de mémorisation servant à stocker temporairement le signal de vérification et un multiplexeur servant à multiplexer le signal de vérification et le signal de données dans le circuit de communication. Un générateur de signaux de base de temps pilote le circuit de communication à un débit supérieur au débit normal, ce qui permet de transmettre le signal de données et le signal de vérification simultanément dans le circuit de communication. Un démultiplexeur reçoit le signal de sortie du circuit de communication et produit un signal de données et un signal de vérification retourné. Un comparateur compare ce dernier avec le signal de vérification stocké dans le circuit de mémorisation et produit un signal indiquant s'ils sont identiques.

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