Reduced speed equalizer

H - Electricity – 04 – L

Patent

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Details

H04L 27/01 (2006.01) H04J 3/06 (2006.01) H04L 25/03 (2006.01) H04N 7/015 (2006.01) H04N 7/12 (2006.01)

Patent

CA 2124709

A reduced speed equalizer is provided which receives signal samples at a first rate but performs the equalizing operation at a second, lower rate which is below the rate at which symbols are transmitted across the channel. The equalizer is clocked to receive samples in a shift register at the first rate. Samples stored in the shift register are clocked into a set of buffers at the second rate. The equalizer coefficients are applied to the samples stored in the buffer set to generate a sequence of equalized symbols at the second rate.

Égaliseur à vitesse réduite permettant de recevoir des échantillons de signaux à une première vitesse mais exécutant l'opération d'égalisation à une deuxième vitesse, moins rapide, inférieure à la vitesse de transmission des symboles sur le canal. L'égaliseur est synchronisé pour recevoir des échantillons dans un registre à décalage à la première vitesse. Les échantillons stockés dans le registre à décalage sont transférés à la cadence d'impulsions d'horloge dans un ensemble de mémoires tampons à la deuxième vitesse. Les coefficients de l'égaliseur sont appliqués aux échantillons stockés dans les mémoires tampons afin de générer à la deuxième vitesse une séquence de symboles égalisés.

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