H - Electricity – 03 – K
Patent
H - Electricity
03
K
H03K 5/26 (2006.01) G01S 19/30 (2010.01) H04B 1/16 (2006.01)
Patent
CA 2681604
A method of processing first and second corresponding signals having a delay therebetween, at least the first signal being a binary signal having chip boundaries, comprises: introducing a plurality of different delays between the first and second signals, successive delay amounts differing from each other by less than the interval between chip boundaries, and for each introduced delay, summing samples of the second signal which are obtained at the times of, at least, chip boundaries between bits of the first signal which have the same state, to obtain a value; thereby to obtain a representation of how the value varies according to the introduced delay, which representation contains a level change associated with an introduced delay which bears a predetermined relationship to the delay between the first and second signals.
L'invention concerne un procédé de traitement de premier et second signaux correspondants ayant un retard entre ceux-ci, au moins le premier signal étant un signal binaire ayant des limites de bribe, lequel procédé comprenant les opérations consistant : à introduire une pluralité de différents retards entre les premier et second signaux, les quantités de retard successives différant les unes des autres de moins de l'intervalle entre les limites de bribe, et pour chaque retard introduit, à additionner des échantillons du second signal qui sont obtenus aux moments, au moins, des limites de bribe entre des bits du premier signal qui ont le même état, pour obtenir une valeur; pour obtenir de cette façon une représentation de la façon dont la valeur varie en fonction du retard introduit, laquelle représentation contient un changement de niveau associé à un retard introduit qui porte une relation prédéterminée au retard entre les premier et second signaux.
Marks & Clerk
Mitsubishi Electric Corporation
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