Systems and methods for generalized slot-to-interlace mapping

H - Electricity – 04 – L

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H04L 5/00 (2006.01) H04W 72/12 (2009.01) H04L 5/02 (2006.01)

Patent

CA 2696443

A transmitter or receiver device includes a processing system configured to have one or more pilot interlace vectors and one or more distance vectors. The processing system is further configured to generate a first slot interlace for a first slot based on the one or more pilot interlace vectors, and is further configured to generate a second slot interlace for a second slot based on the first slot interlace and the one or more distance vectors. Additional slot interlaces for all other slots may also be generated based on the first slot interlace and the one or more distance vectors.

L'invention concerne un dispositif émetteur ou récepteur comprenant un système de traitement configuré pour avoir un ou plusieurs vecteurs d'entrelacement pilote et un ou plusieurs vecteurs de distance. Le système de traitement est en outre configuré pour générer un premier entrelacement de fente pour une première fente en se basant sur les un ou plusieurs vecteurs d'entrelacement pilote et est en outre configuré pour générer un second entrelacement de fente pour une seconde fente en se basant sur le premier entrelacement de fente et les un ou plusieurs vecteurs de distance. Des entrelacements de fente supplémentaires pour toutes les autres fentes peuvent également être générés en se basant sur le premier entrelacement de fente et les un ou plusieurs vecteurs de distance.

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