Method and apparatus for providing two parties transparent...

Details Method and apparatus for providing two parties transparent... Method and apparatus for providing two parties transparent...

G - Physics

06

F

G06F 13/16 (2006.01) G06F 5/10 (2006.01) G06F 15/16 (2006.01) H04L 29/06 (2006.01)

Patent

CA 2079623

A data communication controller having a memory access control unit characterized by a symmetrical access port architecture. The memory access control unit allows both a host processor and the medium access control (MAC) unit of the data communication controller to transparently access a single-port data packet buffer memory while operating a full specified operating speed and without interference between simultaneous memory access requests. The memory access control unit arbitrates asynchronous memory access requests from both the host processor and the medium access control unit, while permitting each of these processors unlimited access to the single-port buffer memory as if it alone had the full memory available to itself at all times. The above capabilities are achieved using automatic address incrementation and data-byte prefetching operations, without requiring the use of a port processor or additional internal data buses.

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