Switching apparatus

H - Electricity – 04 – L

Patent

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Details

H04L 12/56 (2006.01) H04Q 11/04 (2006.01)

Patent

CA 2241683

There is disclosed a switch which allows fair queuing, by assigning a priority value to received data, without requiring time-consuming searches, by storing pointers to the buffer memory in a first memory, and accessing the pointers through a second memory which is in the form of an array, addressable by the priority value. There is further disclosed a system which combines fair queuing and FIFO queuing, to avoid the need for excessive array size.

L'invention concerne un commutateur qui permet une mise en file d'attente équitable en attribuant une valeur de priorité aux données reçues, sans nécessiter des recherches prenant du temps, en enregistrant des pointeurs pour la mémoire tampon dans une première mémoire et en accédant aux pointeurs par une seconde mémoire qui se présente sous la forme d'un système adressable par la valeur de priorité. On décrit, en outre, un système qui combine une mise en file d'attente équitable et une mise en file d'attente du type FIFO, pour éviter que le système n'ait une taille excessive.

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