H - Electricity – 01 – L
Patent
H - Electricity
01
L
H01L 21/60 (2006.01) H01L 23/31 (2006.01) H01L 23/485 (2006.01) H01L 23/538 (2006.01) H01L 25/10 (2006.01)
Patent
CA 2443149
A plurality of semiconductor chips (23) are bonded to an adhesive layer (22) formed on a base plate (21). Then, first to third insulating films (31, 35, 39), first and second underlying metal layers (33, 37), first and second re- wirings (34, 38), and a solder ball (41) are collectively formed for the plural semiconductor chips (23). In this case, the first and second underlying metal layers (33, 37) are formed by a sputtering method, and the first and second re-wirings (34, 38) are formed by an electroplating method. Then, a laminate structure consisting of the three insulating films (39, 35, 31), the adhesive layer (22), and the base plate (21) is cut in a region positioned between the adjacent semiconductor chips (23).
Une pluralité de puces semi-conductrices (23) sont reliées à une couche adhésive (22) formée sur une plaque de base (21). Puis, trois films d'isolation (31, 35, 39), deux couches métalliques (33, 37) sous-jacentes, deux recâblages (34, 38) et une bille de soudure (41) sont collectivement formés pour la pluralité de puces semi-conductrices (23). Dans ce cas, les deux couches métalliques (33, 37) sous-jacentes sont formées au moyen d'un procédé de pulvérisation cathodique, et les deux recâblages (34, 38) sont formés au moyen d'un procédé d'électrodéposition. Enfin, une structure stratifiée composée des trois couches de film isolant (39, 35, 31), de la couche adhésive (22) et de la plaque de base (21) est découpée dans une région positionnée entre les puces semi-conductrices (23) adjacentes.
Mihara Ichiro
Wakabayashi Takeshi
Casio Computer Co. Ltd.
Ridout & Maybee Llp
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