Sense amplifier with improved latching

Details Sense amplifier with improved latching Sense amplifier with improved latching

G - Physics

11

C

G11C 7/06 (2006.01)

Patent

CA 2447650

A sense amplifier (15) that eliminates or substantially attenuates transients at its output node by isolating the output node from the bitline. The sense amplifier incorporates a sense line transistor (50) between the bitline and the output latching circuit in order to strengthen the voltage value at the output node (67) such that it is not affected by the impedance of the bitline. The sense amplifier also consumes less power and is faster because the bitline does not have to be discharged or precharged by the output driver.

L'invention concerne un amplificateur de détection (15) qui élimine ou atténue sensiblement des phénomènes transitoires au niveau de son noeud de sortie en isolant ce dernier de la ligne de bits. L'amplificateur de détection incorpore un transistor de fil de lecture (50) entre la ligne de bits et le circuit de verrouillage de sortie afin de renforcer la valeur de tension au niveau du noeud de sortie (67), de façon à ne pas être affectée par l'impédance de la ligne de bits. L'amplificateur de détection consomme moins d'énergie et est plus rapide puisque la ligne de bits ne requiert pas d'être déchargé ou préchargée par l'excitateur de sortie.

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