Clock recovery circuit with reduced jitter

Details Clock recovery circuit with reduced jitter Clock recovery circuit with reduced jitter

H - Electricity

04

L

H04L 7/027 (2006.01) H03L 7/08 (2006.01) H04L 7/033 (2006.01)

Patent

CA 2150767

A clock recovery circuit has at least two comparators that detect timings at which a digitally modulated signal crosses different levels, and generate level crossing signals at these timings. A classifying circuit classifies sequences of these level crossing signals and issues corresponding classification signals. A timing control circuit generates timing pulses from certain combinations of the level crossing signals and classification signals. A digital phase-locked loop outputs a clock signal synchronized to these timing pulses.

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